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quad, 14-bit, 80 msps/105 msps/125 msps serial lvds 1.8 v analog-to-digital converter data sheet ad9253 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2011C2015 analog devices, inc. all rights reserved. technical support www.analog.com features 1.8 v supply operation low power: 110 mw per channel at 125 msps with scalable power options snr = 74 db (to nyquist) sfdr = 90 dbc (to nyquist) dnl = 0.75 lsb (typical); inl = 2.0 lsb (typical) serial lvds (ansi-644, default) and low power, reduced signal option (similar to ieee 1596.3) 650 mhz full power analog bandwidth 2 v p-p input voltage range serial port control full chip and individual channel power-down modes flexible bit orientation built-in and custom digital test pattern generation multichip sync and clock divider programmable output clock and data alignment programmable output resolution standby mode applications medical ultrasound high speed imaging quadrature radio receivers diversity radio receivers test equipment general description the ad9253 is a quad, 14-bit, 80 msps/105 msps/125 msps analog-to-digital converter (adc) with an on-chip sample- and-hold circuit designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 125 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl-/ cmos-/lvds-compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock output (dco) for capturing data on the output and a frame clock output (fco) for signaling a new output byte are provided. individual-channel power-down is supported and typically consumes less than 2 mw when all channels are disabled. the adc contains several features designed to maximize flexibility and minimize system cost, such functional block diagram ad9253 10065-001 a vdd pdwn drvdd ref select vin?a vin+a vin?b vin+b vin?d vin+d vin?c vin+c sense agnd sync vcm vref d0?a d0+a d0?b d0+b d1?b d1+b d1?c d1+c d0?c d0+c d1?d d1+d dco? dco+ d0?d d0+d fco? fco+ d1?a d1+a clk+ clk? csb sdio/olm sclk/dtp rbias pipeline adc pipeline adc pipeline adc serial lvds digital serializer digital serializer digital serializer digital serializer clock management serial port interface serial lvds serial lvds serial lvds serial lvds serial lvds serial lvds serial lvds pipeline adc 14 14 14 14 1v figure 1. as programmable output clock and data alignment and digital test pattern generation. the available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (spi). the ad9253 is available in a rohs-compliant, 48-lead lfcsp. it is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. small footprint. four adcs are contained in a small, space- saving package. 2. low power of 110 mw/channel at 125 msps with scalable power options. 3. pin compatible to the ad9633 12-bit quad adc. 4. ease of use. a data clock output (dco) operates at frequencies of up to 500 mhz and supports double data rate (ddr) operation. 5. user flexibility. the spi control offers a wide range of flexible features to meet specific system requirements.
ad9253* product page quick links last content update: 09/27/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad9253 evaluation board documentation application notes ? an-1142: techniques for high speed adc pcb layout ? an-501: aperture uncertainty and adc system performance ? an-737: how adisimadc models an adc ? an-742: frequency domain response of switched- capacitor adcs ? an-756: sampled systems and the effects of clock phase noise and jitter ? an-807: multicarrier wcdma feasibility ? an-808: multicarrier cdma2000 feasibility ? an-827: a resonant approach to interfacing amplifiers to switched-capacitor adcs ? an-835: understanding high speed adc testing and evaluation ? an-878: high speed adc spi control software ? an-905: visual analog converter evaluation tool version 1.0 user manual ? an-935: designing an adc transformer-coupled front end data sheet ? ad9253-dscc: military data sheet ? ad9253-ep: enhanced product data sheet ? ad9253: quad, 14-bit, 80 msps/105 msps/125 msps serial lvds 1.8 v analog-to-digital converter user guides ? evaluating the ad9253/ad9633/ad9653 analog-to- digital converters tools and simulations ? visual analog ? ad9253 ibis model reference designs ? cn0249 reference materials technical articles ? ms-2210: designing power supplies for high speed adc tutorials ? mt-230: noise considerations in high speed converter signal chains design resources ? ad9253 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9253 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad9253 data sheet rev. b | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 prod uct highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifica tions .......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing specifications .................................................................. 6 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 ad9253 - 80 .................................................................................. 13 ad9253 - 105 ................................................................................ 15 ad9253 - 125 ................................................................................ 17 equivalent circuit s ......................................................................... 20 theory of operation ...................................................................... 21 analog input considerations .................................................... 21 voltage reference ....................................................................... 22 clock inpu t considerations ...................................................... 23 power dissipation and power - down mode ........................... 25 digital outputs and timing ..................................................... 26 output test modes ..................................................................... 2 9 serial por t interface (spi) .............................................................. 30 configuration using the spi ..................................................... 30 hardware interface ..................................................................... 31 configuration without the spi ................................................ 31 spi accessible features .............................................................. 31 memory map .................................................................................. 32 reading the memory map register table ............................... 32 memory map register table ..................................................... 33 me mory map register descriptions ........................................ 36 applications information .............................................................. 38 design guidelines ...................................................................... 38 power and ground recommendations ................................... 38 clock stability considerations ................................................. 38 exposed pad thermal heat slug recommendations ............ 38 vcm ............................................................................................. 38 reference decoupling ................................................................ 38 spi port ........................................................................................ 38 crosstalk performance .............................................................. 39 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 10/15 rev. a to rev. b add ed note 4, table 4 ...................................................................... 6 changes to digital outputs and timing section ....................... 27 changes to clock stability considerations section ................... 38 9 / 14 rev. 0 to rev. a changes to table 2 ............................................................................ 4 added propagation delay parameters of 1.5 ns ( min ) and 3.1 ns ( max ) ; table 4 , changed t ssync from 0.24 ns typ to 1.2 ns min, and changed t hsync from 0.40 ns typ to ? 0.2 ns m in; table 5 ......................................................................... 6 changes to figure 3 ................................................................................ 7 changes to figure 5 ........................................................................... 8 changes to pin 9 to pin 14 and pin 23 to pin 28 descriptions ...... 1 1 changes to figure 48 and figure 49 ............................................ 2 0 changes to clock input options section .................................... 2 3 changes to jitter considerations section .................................... 2 5 changes to digital outputs and timing section ....................... 2 6 changes to table 11 ....................................................................... 2 8 changes to table 12 ....................................................................... 29 changes to chann el - specific registers section ......................... 3 2 changes to output phase (register 0x16) section .................... 3 6 changes to resolution/sample rate override (register 0x100) section .............................................................................................. 3 7 added clock stability considerations section ........................... 3 8 updated outline dimensions ....................................................... 4 0 10 /11 revision 0: initial version
data sheet ad9253 rev. b | page 3 of 40 specifications dc s pecifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 1 . parameter 1 temp ad9253 - 80 ad9253 - 105 ad9253 - 125 min typ max min typ max min typ max unit resolution 14 14 14 bits accuracy no missing codes full guaranteed guaranteed guaranteed offset error full ? 0.7 ? 0.3 +0.1 ? 0.7 ? 0.3 +0.1 ? 0.7 ? 0.3 +0.1 % fsr offset matching full ? 0.6 +0.2 +0.6 ? 0.6 +0.2 +0.6 ? 0.6 +0.2 +0.6 % fsr gain error full ? 10 ? 5 0 ? 10 ? 5 0 ? 10 ? 5 0 % fsr gain matching full 1 1.6 1 1.6 1.1 1.6 % fsr differential nonlinearity (dnl) full ? 1 +1.6 0.8 +1.5 0.8 +1.5 lsb 25c 0.8 0.75 0.75 lsb integral nonlinearity (inl) full 4.0 +4.0 4.0 4.0 4.0 +4.0 lsb 25c 1.5 2.0 2.0 lsb temperature drift offset error full 2 2 2 ppm/ c internal voltage reference output voltage (1 v mode) full 0.98 1.0 1.02 0.98 1.0 1.02 0.98 1.0 1.02 v load regulation at 1.0 ma (v ref = 1 v) full 2 2 2 mv input resistance full 7.5 7.5 7.5 k input - referred noise v ref = 1.0 v 25c 0.94 0.94 0.94 lsb rms analog inputs differential input voltage (v ref = 1 v) full 2 2 2 v p -p common - mode voltage full 0.9 0.9 0.9 v differential input resistance 5.2 5.2 5.2 k differential input capacitance full 3.5 3.5 3.5 pf power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd 2 full 131 144 158 172 183 200 ma i drvdd (ansi - 644 mode) 2 full 63 81 67 95 71 100 ma i drvdd (reduced range mode) 2 25c 42 48 53 ma total power consumption dc input full 326 375 423 mw sine wave input (four channels including output drivers ansi - 644 mode) full 349 405 405 481 457 540 mw sine wave input (four channels including output drivers reduced range mode) 25c 311 371 425 mw power - down full 2 2 2 mw standby 3 full 178 209 236 mw 1 see the an - 835 application note , understanding high speed adc testing and evalu ation , for definitions and for details on how these tests were completed. 2 measured with a low input frequency, full - scale sine wave on all four channels. 3 can be controlled via the spi.
ad9253 data sheet rev. b | page 4 of 40 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 2 . parameter 1 temp ad9253 - 80 ad9253 - 105 ad9253 - 125 unit min typ max min typ max min typ max signal - to - noise ratio (snr) f in = 9.7 mhz 25c 75.4 75.1 75.3 dbfs f in = 30.5 mhz 25c 74.9 75.0 75.2 dbfs f in = 70 mhz full 72.2 74.7 72.2 74.4 73 74.2 dbfs f in = 140 mhz 25c 72.3 73.1 72.2 dbfs f in = 200 mhz 25c 70.7 71.2 70.7 dbfs signal - to - noise - and - d istortion ratio (sinad) f in = 9.7 mhz 25c 7 5 . 3 7 5.0 75 .2 dbfs f in = 30.5 mhz 25c 74 .8 7 4 .9 75 .1 dbfs f in = 70 mhz full 7 1 .8 7 4.6 70.8 74.2 7 2 .6 7 4 .1 dbfs f in = 140 mhz 25c 72.1 7 2 .8 7 1 .9 dbfs f in = 200 mhz 25c 70.5 70. 8 70.4 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12. 2 12.1 12.2 bits f in = 30.5 mhz 25c 1 2.1 1 2.1 12.1 bits f in = 70 mhz full 11.6 11.9 11.5 12.0 11.8 1 2.0 bits f in = 140 mhz 25c 11.6 11.8 11.6 bits f in = 200 mhz 25c 11.5 11.5 11.4 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 98 98 98 dbc f in = 30.5 mhz 25c 93 92 92 dbc f in = 70 mhz full 77 94 75 89 77 90 dbc f in = 140 mhz 25c 85 85 85 dbc f in = 200 mhz 25c 84 82 83 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ? 98 ? 98 ? 98 dbc f in = 30.5 mhz 25c ? 93 ? 92 ? 92 dbc f in = 70 mhz full ? 94 ? 77 ? 89 ? 75 ? 90 ? 77 dbc f in = 140 mhz 25c ? 85 ? 85 ? 85 dbc f in = 200 mhz 25c ? 84 ? 82 ? 83 dbc worst other (excluding second or third) f in = 9.7 mhz 25c ? 99 ? 9 8 ? 100 dbc f in = 30.5 mhz 25c ? 9 8 9 8 99 dbc f in = 70 mhz full 9 7 77 9 4 77 9 4 84 dbc f in = 140 mhz 25c 9 7 9 7 9 5 dbc f in = 200 mhz 25c 9 4 9 1 9 1 dbc two - tone intermodulation distortion (imd) ? ain1 and ain2 = 7.0 dbfs f in1 = 70.5 mhz, f in2 = 72.5 mhz 25c 90 88 86 dbc crosstalk 2 full 95 95 95 db crosstalk (overrange condition) 3 25c 89 89 89 db power supply rejection ratio (psrr) 1 , 4 avdd 25c 48 48 48 db drvdd 25c 75 75 75 db analog input bandwidth, full power 25c 650 650 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is specified as being 3 db above the full - scale input range. 4 psrr is measured by injecting a sinusoidal signal at 10 mhz to the power supply pin and measuring the ou tput spur on the fft. psrr is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels.
data sheet ad9253 rev. b | page 5 of 40 digital specificatio ns av dd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 3 . parameter 1 temp min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p -p input voltage range full agnd ? 0. 2 avdd + 0.2 v input common - mode voltage full 0.9 v input resistance (differential) 25c 15 k ? input capacitance 25c 4 pf logic inputs (pdwn, sync, sclk) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 30 k ? input capacitance 25c 2 pf logic input (csb) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k ? input capacitance 25c 2 pf logic input (sdio) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k ? input capacitance 25c 5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d 0 x, d 1 x), ansi - 644 logic compliance lvds differential output voltage (v od ) full 290 345 400 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) two s c omplement digital outputs (d0x, d1x), low power, reduced signal option logic compliance lvds differential output voltage (v od ) full 160 200 230 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) twos c omplement 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 this is specified for lvds and lvpecl only. 3 this is specified for 13 sdio/olm pins sharing the same connection.
ad9253 data sheet rev. b | page 6 of 40 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 4 . parameter 1 , 2 temp min typ max unit clock 3 input clock rate full 10 1000 mhz conversion rate 4 full 10 80/105/125 msps clock pulse width high (t eh ) full 6.25/4.76/4.00 ns clock pulse width low (t el ) full 6.25/4.76/4.00 ns output parameters 3 propagation delay (t pd ) full 1.5 2.3 3.1 ns rise time (t r ) (20% to 80%) full 300 ps fall time (t f ) (20% to 80%) full 300 ps fco propagation delay (t fco ) full 1.5 2.3 3.1 ns dco propagation delay (t cpd ) 5 full t fco + (t sample /1 6 ) ns dco to data delay (t data ) 5 full (t sample /1 6 ) ? 300 (t sample /1 6 ) (t sample /1 6 ) + 300 ps dco to fco delay (t frame ) 5 full (t sample /1 6 ) ? 300 (t sample /1 6 ) (t sample /1 6 ) + 300 ps lane delay (t ld ) 90 ps data to data skew (t data - max ? t data - min ) full 50 200 ps wake - up time (standby) 25c 250 ns wake - up time (power- down) 6 25c 375 s pipeline latency full 16 clock cycles aperture aperture delay (t a ) 25c 1 ns aperture uncertainty (jitter , t j ) 25c 1 35 f s rms out - of - range recovery time 25c 1 c lock cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured on standard fr - 4 material. 3 can be adjusted via the spi. the conversion r ate is the clock rate after the divider. 4 the maximum conversion rate is based on two - lane output mode. see the digital outputs and timing section for the maximum conversion rate in one - lane output mode. 5 t sample /16 is based on the number of bits in two lvds data lanes. t sample = 1/f s . 6 wake - up time is defined as the time requ ired to return to normal operation from power - down mode. timing specification s table 5 . parameter description limit unit sync timing requirements t ssync sync to rising edge of clk+ setup time 1.2 ns m in t hsync sync to rising edge of clk+ hold time ? 0.2 ns m in spi timing requirements see figure 74 t ds setup time between the data and the rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 74) 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 74) 10 ns min
data sheet ad9253 rev. b | page 7 of 40 timing diagrams refer to the memory map register descriptions section and table 21 for spi register settings. d0?a d0+a d1?a d1+a fco? bytewise mode fco+ d0?a d0+a d1?a d1+a fco? dco? dco+ dco+ clk+ vinx clk? dco? fco+ bitwise mode sdr ddr 10065-003 msb n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 msb n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 0 n ? 16 0 n ? 16 msb n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 0 n ? 17 msb n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 0 n ? 16 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 0 n ? 17 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 0 n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n n + 1 figure 2. 16-bit ddr/sdr, two-lane, 1 frame mode (default) 10065-004 d0?a d0+a d1?a d1+a fco? bytewise mode fco+ d0?a d0+a d1?a d1+a fco? dco? clk+ clk? dco+ dco? dco+ fco+ bitwise mode sdr ddr d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx t a n ? 1 n n + 1 figure 3. 12-bit ddr/sdr, two-lane, 1 frame mode
ad9253 data sheet rev. b | page 8 of 40 10065-005 d0?a d0+a d1?a d1+a fco? bytewise mode fco+ d0?a d0+a d1?a d1+a fco? dco? dco+ dco+ clk+ vinx clk? dco? fco+ bitwise mode sdr ddr msb n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 msb n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 0 n ? 16 0 n ? 16 msb n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 0 n ? 17 msb n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 0 n ? 16 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 0 n ? 17 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 0 n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n n + 1 figure 4. 16-bit ddr/sdr, two-lane, 2 frame mode 10065-006 d0?a d0+a d1?a d1+a fco? bytewise mode fco+ d0?a d0+a d1?a d1+a fco? dco? clk+ clk? dco+ fco+ bitwise mode sdr ddr dco? dco+ d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld vinx t a n ? 1 n n + 1 t el figure 5. 12-bit ddr/sdr, two-lane, 2 frame mode
data sheet ad9253 rev. b | page 9 of 40 10065-002 d0?x d0+x fco? dco+ clk+ vinx clk? dco? fco+ d12 n ? 17 msb n?17 d11 n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n figure 6. wordwise ddr, one-lane , 1 frame, 16-bit output mode 10065-082 d0?x d0+x fco? dco+ clk+ vinx clk? dco? fco+ d10 n ? 17 msb n?17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 d0 n ? 17 msb n ? 16 d10 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n figure 7. wordwise ddr, one-lane, 1 frame, 12-bit output mode s yn c clk+ t hsync t ssync 10065-079 figure 8. sync input timing requirements
ad9253 data sheet rev. b | page 10 of 40 absolute maximum rat ings table 6 . parameter rating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ? 0.3 v to +2.0 v digital outputs (d0x, d1x, dco+, dco?, fco+, fco?) to agnd ? 0.3 v to +2.0 v clk+, clk? to agnd ? 0.3 v to +2.0 v vin +x, vin ? x to agnd ? 0.3 v to +2.0 v sclk /dtp , sdio /olm , csb to agnd ? 0.3 v to +2.0 v sync, pdwn to agnd ? 0.3 v to +2.0 v rbias to agnd ? 0.3 v to +2.0 v vref, sense to agnd ? 0.3 v to +2.0 v environmental operating temperature range (ambient) ? 40 c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ? 65c to +150 c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation b eyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance table 7 . thermal resistance package type air flow velocity (m/sec) ja 1 jb jc unit 48- lead lfcsp 0.0 23.7 7.8 7.1 c/w 7 mm 7 mm 1.0 20.0 n/a n/a c/w (cp -48- 13) 2.5 18.7 n/a n/a c/w 1 ja for a 4 - layer pcb with solid ground plane (simulated). exposed pad soldered to pcb. esd caution
data sheet ad9253 rev. b | page 11 of 40 pin configuration and fu nction descriptions 1 2 3 vin+a vin?a avdd 4 pdwn 5 csb 6 sdio/olm 7 sclk/dtp 2 4 d 0 + b 2 3 d 0 ? b 2 2 d 1 + b 2 1 d 1 ? b 2 0 f c o + 1 9 f c o ? 1 8 d c o + 1 7 d c o ? 1 6 d 0 + c 1 5 d 0 ? c 1 4 d 1 + c 1 3 d 1 ? c 4 4 s y n c 4 5 a v d d 4 6 a v d d 4 7 v i n ? c 4 8 v i n + c 4 3 v c m 4 2 v r e f 4 1 s e n s e 4 0 r b i a s 3 9 a v d d 3 8 v i n ? b 3 7 v i n + b 25 d0+d 26 d0?d 27 d1+d 28 d1?d 29 drvdd 30 avdd 31 clk+ 32 clk? 33 avdd 34 avdd 35 vin?d 36 vin+d 8 drvdd 9 d0+a 10 d0?a 11 d1+a 12 d1?a 10065-007 ad9253 top view (not to scale) notes 1. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. figure 9. 48-lead lfcsp pin configuration, top view table 8. pin function descriptions pin no. mnemonic description 0 agnd, exposed pad analog ground, exposed pad. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 1 vin+d adc d analog input true. 2 vin?d adc d analog input complement. 3, 4, 7, 34, 39, 45, 46 avdd 1.8 v analog supply pins. 5, 6 clk?, clk+ differential encode clock. pecl, lvds, or 1.8 v cmos inputs. 8, 29 drvdd digital output driver supply. 9, 10 d1?d, d1+d channel d digital outputs, (disabled in one-lane mode 1 ). 11, 12 d0?d, d0+d channel d digital outputs, (disabled in one-lane mode 1 ). 13, 14 d1?c, d1+c channel c digital outputs, (cha nnel d digital outputs in one-lane mode 1 ). 15, 16 d0?c, d0+c channel c digital outputs. 17, 18 dco?, dco+ data clock outputs. 19, 20 fco?, fco+ frame clock outputs. 21, 22 d1?b, d1+b channel b digital outputs. 23, 24 d0?b, d0+b channel b digital outputs, (cha nnel a digital outputs in one-lane mode 1 ). 25, 26 d1?a, d1+a channel a digital outputs, (disabled in one-lane mode 1 ). 27, 28 d0?a, d0+a channel a digital outputs, (disabled in one-lane mode 1 ). 30 sclk/dtp spi clock input/digital test pattern. 31 sdio/olm spi data input and output bi directional spi data/output lane mode. 32 csb spi chip select bar. active low enable; 30 k internal pull-up. 33 pdwn digital input, 30 k internal pull-down. pdwn high = power-down device. pdwn low = run device, normal operation. 35 vin?a adc a analog input complement. 36 vin+a adc a analog input true. 37 vin+b adc b analog input true. 38 vin?b adc b analog input complement. 40 rbias sets analog current bias. connect to 10 k (1% tolerance) resistor to ground. 41 sense reference mode selection. 42 vref voltage reference input and output. 43 vcm analog input common-mode voltage.
ad9253 data sheet rev. b | page 12 of 40 pin no. mnemonic description 44 sync digital input. sync input to clock divider. 47 vin?c adc c analog input complement . 48 vin + c adc c analog input true . 1 output channel assignments are shown first for default two - lane mode. if one - lane mode is used, output channel assignments change as indicated in parenthesis. register 0x21 bits[6:4] invoke one - lan e mode.
data sheet ad9253 rev. b | page 13 of 40 typical performance characteristics ad9253 - 80 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 5 15 20 25 30 40 35 amplitude (dbfs) frequency (mhz) 10065-016 ain = ?1dbfs snr = 75.5db enob = 12.07bits sfdr = 99.3dbc figure 10 . single - tone 16k fft with f in = 9.7 mhz, f sample = 80 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 5 15 20 25 30 40 35 amplitude (dbfs) frequency (mhz) 10065-089 ain = ?1dbfs snr = 73.9db enob = 11.9 bits sfdr = 92.7dbc figure 11 . single - tone 16k fft with f in = 30.5 mhz, f sample = 80 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 5 15 20 25 30 40 35 amplitude (dbfs) frequency (mhz) 10065-017 ain = ?1dbfs snr = 74.7db enob = 11.9 bits sfdr = 94.2dbc figure 12 . single - tone 16k fft with f in = 70 mhz, f sample = 80 msps 10 5 15 20 25 30 40 35 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 amplitude (dbfs) frequency (mhz) 10065-018 ain = ?1 dbfs snr = 72.3db enob = 11.5 bits sfdr = 85dbc figure 13 . single - tone 16k fft with f in = 140 mhz, f sample = 80 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 5 15 20 25 30 40 35 amplitude (dbfs) frequency (mhz) 10065-019 ain = ?1dbfs snr = 70.7db enob = 11.3 bits sfdr = 83.7dbc figure 14 . single - tone 16k fft with f in = 200 mhz, f sample = 80 msps 120 ?20 ?100 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) 10065-030 sfdrfs sfdr snrfs snr 0 20 40 60 80 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 figure 15 . snr/sfdr vs. analog input level, f in = 9.7 mhz, f sample = 80 msps
ad9253 data sheet rev. b | page 14 of 40 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 5 15 20 25 30 40 35 amplitude (dbfs) frequency (mhz) 10065-033 ain1 and ain2 = ?7dbfs sfdr = 90.9dbc imd2 = 91dbc imd3 = 90.9dbc figure 16 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 80 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?6 ?18 ?30 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) 10065-036 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 17 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 80 msps 100 0 0 200 snr/sfdr (dbfs/dbc) input frequency (mhz) 10065-039 70 10 20 30 40 50 60 80 90 100 120 140 80 20 40 60 180 160 sfdr (dbc) snr (dbfs) figure 18 . snr/sfdr vs. f in , f sample = 80 msps 105 70 ?40 85 snr/sfdr (dbfs/dbc) temperature (c) 10065-042 75 80 85 90 95 100 ?15 10 35 60 sfdr (dbc) snr (dbfs) figure 19 . snr/sfdr vs. temperature, f in = 10.3 mhz, f sample = 80 msps
data sheet ad9253 rev. b | page 15 of 40 ad9253 - 105 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 amplitude (dbfs) frequency (mhz) 10065-020 ain = ?1dbfs snr = 75.1db enob = 12.02 bits sfdr = 97.8dbc figure 20 . single - tone 16k fft with f in = 9.7 mhz, f sample = 105 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 amplitude (dbfs) frequency (mhz) 10065-090 ain = ?1dbfs snr = 74db enob = 11.9 bits sfdr = 92.1dbc figure 21 . single - tone 16k fft with f in = 30.5 mhz, f sample = 105 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 amplitude (dbfs) frequency (mhz) 10065-021 ain = ?1dbfs snr = 73.4db enob = 11.9 bits sfdr = 89.8dbc figure 22 . single - tone 16k fft with f in = 70 mhz, f sample = 105 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 amplitude (dbfs) frequency (mhz) 10065-022 ain = ?1dbfs snr = 73.1db enob = 11.6 bits sfdr = 85dbc figure 23 . single - tone 16k fft with f in = 140 mhz, f sample = 105 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 amplitude (dbfs) frequency (mhz) 10065-023 ain = ?1dbfs snr = 71.2db enob = 11.3 bits sfdr = 82dbc figure 24 . single - tone 16k fft with f in = 200 mhz, f sample = 105 msps 120 ?20 ?100 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) 10065-031 sfdrfs sfdr snrfs snr 0 20 40 60 80 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 figure 25 . snr/sfdr vs. analog input level, f in = 9.7 mhz, f sample = 105 msps
ad9253 data sheet rev. b | page 16 of 40 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 amplitude (dbfs) frequency (mhz) 10065-034 ain1 and ain2 = ?7dbfs sfdr = 87.5dbc imd2 = 92.6dbc imd3 = 87.5dbc figure 26 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 105 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?6 ?18 ?30 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) 10065-037 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 27 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 105 msps snr/sfdr (dbfs/dbc) input frequency (mhz) 10065-040 sfdr (dbc) snr (dbfs) 100 0 0 200 70 10 20 30 40 50 60 80 90 100 120 140 80 20 40 60 180 160 figure 28 . snr/sfdr vs. f in , f sample = 105 msps 100 70 ?40 85 snr/sfdr (dbfs/dbc) temperature (c) 10065-043 75 80 85 90 95 ?15 10 35 60 sfdr (dbc) snr (dbfs) figure 29 . snr/sfdr vs. temperature, f in = 10.3 mhz, f sample = 105 msps
data sheet ad9253 rev. b | page 17 of 40 ad9253 - 125 10065-024 ain = ?1dbfs snr = 75.3db enob = 12.04 bits sfdr = 98.52dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) figure 30 . single - tone 16k fft with f in = 9.7 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) 10065-091 ain = ?1dbfs snr = 74.2db enob = 12 bits sfdr = 92.5dbc figure 31 . single - tone 16k fft with f in = 30.5 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) 10065-025 ain = ?1dbfs snr = 73.2db enob = 11.9 bits sfdr = 91.2dbc figure 32 . single - tone 16k fft with f in = 70 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) 10065-026 ain = ?1dbfs snr = 73.1db enob = 11.6 bits sfdr = 85dbc figure 33 . single - tone 16k fft with f in = 140 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) 10065-027 ain = ?1dbfs snr = 70.6db enob = 11.2 bits sfdr = 83.2dbc figure 34 . single - tone 16k fft with f in = 200 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) 10065-081 a in = ?1dbfs snr = 72.4db enob = 11.7 bits sfdr = 88.4dbc figure 35 . single - tone 16k fft with f in = 140 mhz at f sample = 122.88 msps
ad9253 data sheet rev. b | page 18 of 40 120 0 ?100 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) 10065-032 sfdrfs sfdr snrfs snr 20 40 60 80 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 figure 36 . snr/sfdr vs. analog input level, f in = 9.7 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 60 50 amplitude (dbfs) frequency (mhz) 10065-035 ain1 and ain2 = ?7dbfs sfdr = 86.2dbc imd2 = 98.3dbc imd3 = 86.2dbc figure 37 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?6 ?18 ?30 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) 10065-038 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 38 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps snr/sfdr (dbfs/dbc) input frequency (mhz) 10065-041 100 0 0 200 70 10 20 30 40 50 60 80 90 100 120 140 80 20 40 60 180 160 snr (dbfs) sfdr (dbc) figure 39 . snr/sfdr vs. f in , f sample = 125 msps 100 70 ?40 85 snr/sfdr (dbfs/dbc) temperature (c) 10065-044 75 80 85 90 95 ?15 10 35 60 sfdr (dbc) snr (dbfs) figure 40 . snr/sfdr vs. temperature, f in = 10.3 mhz, f sample = 125 msps 2.5 ?2.5 0 16000 inl (lsb) output code 10065-045 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2000 4000 6000 8000 10000 12000 14000 figure 41 . inl, f in = 9.7 mhz, f sample = 125 msps
data sheet ad9253 rev. b | page 19 of 40 1.0 ?1.0 0 16000 dnl (lsb) output code 10065-046 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 2000 4000 6000 8000 10000 12000 14000 figure 42 . dnl, f in = 9.7 mhz, f sample = 125 msps 500,000 450,000 400,000 350,000 300,000 250,000 200,000 0 50,000 100,000 150,000 n ? 4 n ? 3 n ? 2 n ? 1 n + 1 n + 2 n + 3 n + 4 n + 5 n number of hits code 10065-050 0.94 lsb rms figure 43 . input - referred noise histogram, f sample = 125 msps 100 0 1 10 psrr (db) frequency (mhz) 10065-087 10 20 30 40 50 60 70 80 90 avdd drvdd figure 44 . psrr vs. frequency, f clk = 125 mhz , f sample = 125 msps 105 65 20 45 70 95 120 snr/sfdr (dbfs/dbc) sample frequency (msps) 10065-028 70 75 80 85 90 95 100 sfdr snrfs figure 45 . snr/sfdr vs. encode, f in = 9.7 mhz , f sample = 125 msps 105 65 20 45 70 95 120 snr/sfdr (dbfs/dbc) sample frequency (msps) 10065-029 70 75 80 85 90 95 100 snrfs sfdr figure 46 . snr/sfdr vs. encode, f in = 70 mhz , f sample = 125 msps
ad9253 data sheet rev. b | page 20 of 40 equivalent circuits a vdd vinx 10065-008 figure 47 . equivalent analog input circuit 10065-009 clk+ clk? 0.9v 15k? 10? 10? 15k? a vdd a vdd figure 48 . equivalent clock input circuit 10065-010 31k? sdio/olm 400? a vdd figure 49 . equivalent sdio/olm input circuit d r vdd drgnd d0?x, d1?x d0+x, d1+x v v v v 10065-0 1 1 figure 50 . equivalent digital output circuit 350? a vdd 30k? sclk/dt p , sync, and pdwn 10065-012 figure 51 . equivalent sclk /dtp , sync , and pdwn input circuit rbias and vcm 375? a vdd 10065-013 figure 52 . equivalent rbias and vcm circuit csb 350? a vdd 30k? 10065-014 figure 53 . equivalent csb input circuit vref 10065-015 a vdd 7.5k? 375?
data sheet ad9253 rev. b | page 21 of 40 theory of operation the ad9253 is a multistage, pipelined adc . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. the serializer transmits this converted data in a 16 - bit output. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, c onsists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier (for example, a multiplying digital - to - analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac ou tput and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects err ors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. analog input conside rations the analog input to the ad9253 is a differential s witched - capacitor circuit designed for processing differential input signals. this circuit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsupply, users can minimize signal - dependent errors and achieve optimum performance. s s h c par c sample c sample c par v i n?x h s s h v i n+x h 10065-051 figure 55 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 5 5 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current i njected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a differential capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ult imately creates a low - pass filter at the input to limit unwanted broadband noise. see the an - 742 application note , the an - 827 applicatio n note , and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise val ues depend on the application. input common mode the analog inputs of the ad9253 are not internally dc - biased. therefore, in ac - coupled applications, the user must provide this bias externally. s etting the device so that v cm = av dd /2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in figure 56. an on - chip , common - mode voltage reference is included in the design and is available from the vcm pin. the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9253 , the largest input span available is 2 v p - p. 100 20 0.5 snr/sfdr (dbfs/dbc) v cm (v) 10065-052 30 40 50 60 70 80 90 0.7 0.9 1.1 1.3 snrfs sfdr figure 56 . snr/sfdr vs. common - mode voltage, f in = 9.7 mhz, f sample = 125 msps
ad9253 data sheet rev. b | page 22 of 40 differential input configurations there are several ways to drive the ad9253 either actively or passively. however, optimum performance is achieved by driving the analog inputs differentially. using a differential double balun configuration to drive the ad9253 provides excellent performance and a flexible interface to the adc (see figure 58) for baseband applications. for applications where snr is a key parameter, differential trans- former coupling is the recommended input configuration (see figure 59), because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9253. regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is not recommended to drive the ad9253 inputs single-ended. voltage reference a stable and accurate 1.0 v voltage reference is built into the ad9253 . vref can be configured using either the internal 1.0 v reference or an externally applied 1.0 v reference voltage. the various reference modes are summarized in the internal reference connection section and the external reference operation section. the vref pin should be externally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. internal reference connection a comparator within the ad9253 detects the potential at the sense pin and configures the reference into two possible modes, which are summarized in table 9. if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 57), setting vref to 1.0 v. table 9. reference configuration summary selected mode sense voltage (v) resulting vref (v) resulting differential span (v p-p) fixed internal reference agnd to 0.2 1.0 internal 2.0 fixed external reference avdd 1.0 applied to external vref pin 2.0 vref sense 0.5v adc select logic 0.1f 1.0f vin?a/vin?b vin+a/vin+b adc core 10065-060 figure 57. internal reference configuration adc r 0.1f 0.1f 2v p-p vcm c *c1 *c1 c r 0.1f 0.1f 0.1f 33 ? 200 ? 33 ? 33 ? 33 ? vin+x vin?x 10065-059 et1-1-i3 c c 5pf r *c1 is optional figure 58. differential double balun input configuration for base band applications 2v p-p r r *c1 *c1 is optional 49.9 ? 0.1 f a dt1-1wt 1:1 z ratio vin?x adc vin+x *c1 c vcm 10065-056 33 ? 33 ? 200 ? 0.1f 5pf figure 59. differential transformer-coupled configuration for baseband applications
data sheet ad9253 rev. b | page 23 of 40 if the internal reference of the ad9253 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 60 shows how the internal reference voltage is affected by loading. 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 0 3.0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) 10065-061 interna l v ref = 1v figure 60 . v ref error vs. load current external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac - teristics. figure 61 shows the typical drift characteristics of the internal reference in 1.0 v mode. 4 ?8 ?40 85 v ref error (mv) temperature (c) 10065-062 ?6 ?4 ?2 0 2 ?15 10 35 60 figure 61 . typical v ref drift when the sense pin is tied to avdd, the internal refe rence is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7.5 k? load (see figure 54 ). the internal buffer generates the positive and negative full - scale references for the adc core. there - fore, the external reference must be limited to a maximum of 1.0 v. it is not recommended to leave the sense pin floating. clock input co nsiderations for optimum performance, clock the ad9253 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac - coupled into the clk+ and clk? pins via a transfo rmer or capacitors. these pins are biased internally (see figure 48 ) and require no external bias. clock input options th e ad9253 has a flexible clock input structure. the clock in put can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern , as described in the jitter considerations section. figure 62 and figure 63 show two preferred methods for clock - ing the ad9253 ( at clock rates up to 1 ghz prior to internal clk divider). a low jitter clock source is converted from a single - ended signal to a differential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock freque ncies between 125 mhz and 1 ghz, and the rf transformer is recom - me nded for clock frequencies from 10 mhz to 200 mhz. the anti parallel sch ottky diodes across the transformer/balun secondary winding limit clock excursions into the ad9253 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9253 while preserving the fast rise and fall times of the signal that are critical to a chieving low jitter performance. however, the diode capacitance comes into play at frequencies above 500 mhz. care must be taken in choosing the ap propriate signal limiting diode. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 10065-064 figure 62 . transformer - coupled differential clock (up to 200 mhz) 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 10065-065 figure 63 . balun - coupled differential clock (up to 1 ghz) if a low jitter clock source is not availab le, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 65 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 -0 / ad9516 -1 / ad9516 -2 / ad9516 -3 / ad9516 -4 / ad9516 -5 / ad9517 -0 / ad9517 -1 / ad9517 -2 / ad9517 -3 / ad9517 -4 clock drivers offer excellent jitter performance. a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 66 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 -0 / ad9516 -1 / ad9516 -2 / ad9516 -3 / ad9516 -4 / ad9516 -5 / ad9517 -0 / ad9517 -1 / ad9517 -2 / ad9517 -3 / ad9517 -4 clock drivers offer excellent jitter performance.
ad9253 data sheet rev. b | page 24 of 40 in some applications, it may be acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 67 ). input clock divider the ad9253 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. the ad9253 clock divider can be synchronized using the external sync input. bit 0 and bit 1 of register 0x109 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling . clock duty cycle t ypical high speed adcs use both clock edges to generate a vari - ety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characterist ics. the ad9253 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provi de a wide range of clock input duty cycles without affecting the performance of the ad9253 . noise and distortion perform - ance are nearly flat for a wide range of duty cycles with the dcs on, as sh own in figure 64 . 80 55 40 60 snrfs (dbfs) duty cycle (%) 10065-069 60 65 70 75 42 44 46 48 50 52 54 56 58 snrfs (dcs off) snrfs (dcs on) figure 64 . snr vs. dcs on/off jitter in the rising edge of the input is still of concern and is not easi ly reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50k? 50k? clk? clk+ clock input clock input adc ad951x pecl driver 10065-066 figure 65 . differential pecl sample clock (up to 1 ghz) 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ adc clock input clock input ad951x lvds driver 10065-067 figure 66 . differential lvds sample clock (up to 1 ghz) optional 100? 0.1f 0.1f 0.1f 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? clock input ad951x cmos driver 10065-068 figure 67 . single - ended 1.8 v cmos input clock (up to 200 mhz)
data sheet ad9253 rev. b | page 25 of 40 jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calculated by snr degradation = 20 log 10 ? ? ? ? ? ? ? ? j a t f 2 1 in this equation , the rms aperture jitter represents the root sum square of all jitter sources, including the clock input, analog in put signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 68). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9253 . power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators make the best cl ock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an - 501 applica tion note and the an - 756 application note for more in - depth information about jitter performance as it relates to adcs. 1 10 100 1000 16 b i t s 14 b i t s 12 b i t s 30 40 50 60 70 80 90 100 1 10 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps a n a l og i npu t f re qu e n c y ( m h z) 10 bits 8 bits rms clock jitter requirement snr (db) 10065-070 figure 68 . ideal snr vs. input frequency and jitt er power dissipation an d power - down mode as shown in figure 69, the power dissipated by the ad9253 is proportional to its sample rate. the digital power dissipation does not vary significantly be cause it is determined primarily by the drvdd supply and bias current of the lvds output drivers. 350 300 250 200 150 100 10 130 analog core power (mw) sample rate (msps) 10065-071 20 30 40 50 60 70 80 90 100 110 120 50 msps 80 msps 125 msps 40 msps 20 msps 65 msps 105 msps figure 69 . analog core power vs. f sample for f in = 10.3 mhz the ad9253 is placed in power - down mode either by the spi port or by asserting the pdwn pin high. in this state, the adc typically dissipates 2 mw. during power - down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad9253 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power - down mode and then must be recharged when returning to normal operation. as a result, wake - up time is related to the time spent in power - down mode, and shorter power - down cycles result in proportionally shorter wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the inte rnal reference circuitry powered when faster wake - up times are required. see the memory map section for more details on using these features.
ad9253 data sheet rev. b | page 26 of 40 digital outputs and timing the ad9253 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p-p differential) at the receiver. when operating in reduced range mode, the output current is reduced to 2 ma. this results in a 200 mv swing (or 400 mv p-p differential) across a 100 termination at the receiver. the ad9253 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. if there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. an example of the fco and data stream with proper trace length and position is shown in figure 70. figure 71 shows the lvds output timing example in reduced range mode. 10065-074 d0 500mv/div d1 500mv/div dco 500mv/div fco 500mv/div 4ns/div figure 70. ad9253-125, lvds output timing example in ansi-644 mode (default) 10065-083 d0 400mv/div d1 400mv/div dco 400mv/div fco 400mv/div 4ns/div figure 71. ad9253-125, lvds output timing example in reduced range mode an example of the lvds output using the ansi-644 standard (default) data eye and a time interval error (tie) jitter histo- gram with trace lengths less than 24 inches on standard fr-4 material is shown in figure 72. 6k 7k 1k 2k 3k 5k 4k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps tie jitter histogram (hits) 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns 0.8ns eye diagram voltage (mv) eye: all bits uls: 7000/400354 10065-075 figure 72. data eye for lvds outputs in ansi-644 mode with trace lengths less than 24 inches on standard fr-4 material, external 100 far-end termination only
data sheet ad9253 rev. b | page 27 of 40 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns ?0.8ns eye diagram voltage (mv) eye: all bits uls: 8000/414024 10k 12k 2k 4k 6k 8k 0k ?800ps ?600ps ?400ps ?200ps 0ps 200ps 400ps 600ps tie jitter histogram (hits) 10065-076 figure 73. data eye for lvds outputs in ansi-644 mode with trace lengths greater than 24 inches on standard fr-4 material, external 100 far-end termination only figure 73 shows an example of trace lengths exceeding 24 inches on standard fr-4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the users responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (increasing the current) of all four outputs to drive longer trace lengths. this can be achieved by programming register 0x15. even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when this option is used. the format of the output data is twos complement by default. an example of the output coding format can be found in table 10. to change the output data format to offset binary, see the memory map section. data from each adc is serialized and provided on a separate channel in two lanes in ddr mode. the data rate for each serial stream is equal to 16 bits times the sample clock rate divided by the number of lanes, with a maximum of 1000 mbps/lane [(16 bits 125 msps)/2 = 1000 mbps/lane)]. the maximum allowable output data rate is 1 gbps/lane. if one-lane mode is used, the data rate doubles for a given sample rate. to stay within the maximum data rate of 1 gbps/lane, the sample rate is limited to a maximum of 62.5 msps in one-lane output mode. the lowest typical conversion rate is 10 msps. two output clocks are provided to assist in capturing data from the ad9253 . the dco is used to clock the output data and is equal to four times the sample clock (clk) rate for the default mode of operation. data is clocked out of the ad9253 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. the fco is used to signal the start of a new output byte and is equal to the sample clock rate in 1 frame mode. see the timing diagrams section for more information. table 10. digital output coding input (v) condition (v) offset binary output mode twos complement mode vin+ ? vin? +vref ? 0.5 lsb 1111 1111 1111 1100 0111 1111 1111 1100
ad9253 data sheet rev. b | page 28 of 40 table 11 . flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select notes 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 (12 - bit) 1000 0000 0000 0000 (1 6 - bit) n/a yes offset binary code shown 0010 +full - scale short 1111 1111 1111 (12 - bit) 1111 1111 1111 11 00 (1 6 - bit) n/a yes offset binary code shown 0011 ? full - scale short 0000 0000 000 0 (12 - bit) 0000 0000 0000 0000 (16 - bit) n/a yes offset binary code shown 0100 checkerboard 1010 1010 101 0 (12 - bit) 1010 1010 1010 10 0 0 (16 - bit) 0101 0101 0101 (12 - bit) 0101 0101 0101 010 0 (1 6 - bit) no 0101 pn sequence long 1 n/a n/a yes pn23 itu 0 .150 x 23 + x 18 + 1 0110 pn sequence short 1 n/a n/a yes pn9 itu 0 .150 x 9 + x 5 + 1 0111 one - /zero - word toggle 1111 1111 1111 (12 - bit) 11 1 1111 1111 1100 ( 16- bit) 0000 0000 0000 (12 - bit) 0000 0000 0000 0000 (1 6 - bit) no 1000 user input register 0x19 to register 0x1a register 0x1b to register 0x1c no 1001 1 -/0 - bit toggle 1010 1010 1010 (12 - bit) 1010 1010 1010 10 0 0 ( 16 - bit) n/a no 1010 1 sync 0000 0011 1111 (12 - bit) 0000 000 1 111 1 11 00 ( 16 - bit) n/a no 1011 one bit high 1000 0000 0000 (12 - bit) 1000 0000 0000 0000 ( 16 - bit) n/a no pattern associated with the external pin 1100 mixed frequency 1010 0011 0011 (12 - bit) 10 10 000 1 1001 1100 (1 6 - bit) n/a no 1 all test mode options except pn sequence short and pn sequence long can support 12 - bit to 16 - bit word lengths to verify data capture to the receiver. when the spi is use d, the dco phase can be adjusted in 6 0 increments relative to one data cycle (30 relative to one dco cycle) . this enables the user to refine system timing margins if required. the default dco to output data edge timing, as shown in figure 2 , is 180 relative to one data cycle (90 relative to one dco cycle) . a 12 - bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lo wer resolution systems. when changing the resolution to a 12 - bit serial stream, the data stream is shortened. see figure 3 for the 12- bit example. how ever, in the default option with the s erial o utput n umber of b its at 16, the data stream stuffs two 0s at the end of the 14 - bit serial data. in default mode, as shown in figure 2 , the msb is first in the data output serial stream. this can be inverted so that the lsb is first in the data output serial stream by using the spi . there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 11 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns do not adhere to th e data format select option. in addition, custom user - defined test patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bi ts. a description of the pn sequence and how it is generated can be found in section 5.1 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 12 for the initial values). the output is a parallel representation of the serial pn9 sequence in msb - first format. the first output word is the first 14 bits of the pn9 sequence in msb aligned form. the pn sequence long pattern produces a ps eudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 12 for the initial values) and the ad9253 inverts the bit stream with relation to the itu standard. the output is a parallel represent ation of the serial pn23 sequence in msb - first format. the first output word is the first 14 bits of the pn23 sequence in msb aligned form
data sheet ad9253 rev. b | page 29 of 40 table 12 . pn sequence sequence initial value next three output samples (m sb first) twos comple ment pn sequence short 0x1fe0 0x1df1, 0x3cc8, 0x294e pn sequence long 0x1fff 0x1fe0, 0x2001, 0x1c00 consult the memory map section for information on how to change these additional digital output timing features through the spi. sdio/o l m pin for applications that do not require spi mode operation, the csb pin is tied to avdd , and the sdio/olm pin controls the o utput l ane m ode according to table 13. for applications where this pin is not used, csb should be t ied to avdd. when using the one - lane mode, the encode rate should be 62.5 msps to meet the maximum output rate of 1 gbps. table 13 . output lane mode pin settings olm pin voltage output mode avdd (default) two -l ane. 1 frame , 16 -b it s erial o utput gnd one -l ane. 1 f rame, 16- bit serial output sclk/dtp pin the sclk/dtp pin is for use in applications that do not require spi mode operation. this pin can enable a single digital test pattern if it and the csb pin are held high during device power - up. when sclk/dtp is tied to avdd, the adc channel outputs shift out the following pattern: 1000 0000 0000 0000. the fco and dco function normally while all channels shift out the repeatable test pattern. this pattern allows the user to perfor m timing alignment adjustments among the fco, dco, and output data. this pin has an internal 10 k? resistor to gnd. it can be left unconnected. table 14 . digital test pattern pin settings selected dtp dtp voltage resulting d0x and d1x normal operation 10 k? to agnd normal operation dtp avdd 1000 0000 0000 0000 additional and custom test patterns can also be observed when commanded from the spi port. consult the memory map section for information about the options available. csb pin the csb pin should be tied to avdd for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. rbias pin to set the internal core bias current of the adc, place a 10.0 k ?, 1% tolerance resistor to ground at the rbias pin. output test modes the output test options are described in table 1 1 and controlled by the output test mode bits at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks and the te st pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be pe rformed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an - 877 application note , interfacing to high speed adcs via spi .
ad9253 data sheet rev. b | page 30 of 40 serial port interface (spi) the ad9253 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi offers the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu- mented in the memory map section. for detailed operational information, see the an-877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 15). the sclk (a serial clock) is used to synchronize the read and write data presented from and to the adc. the sdio (serial data input/output) is a dual- purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb (chip select bar) is an active low control that enables or disables the read and write cycles. table 15. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data inp ut/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 74 and table 5. other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. all data is composed of 8-bit words. data can be sent in msb- first mode or in lsb-first mode. msb-first mode is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note , interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 10065-078 figure 74. serial port interface timing diagram
data sheet ad9253 rev. b | page 31 of 40 hardware interface the pins described in table 15 comprise the physical interface between the user programming device and the serial port of the ad9253 . the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , micro - controller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9253 to prevent these signals from transi - tioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device power - on, they are as sociated with a specific function. table 16 describes the strappable functions supported on the ad9253 . configuration withou t the spi in applications that do not interface to the spi control registers, the sdio/o l m pin, the sclk/dtp pin, and the pdwn pin serve as standalone cmos - compatible co ntrol pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, and power - down feature control. in this mode, csb should be connected to avdd, which d isables the serial port interface. when the device is in spi mode, the pdwn pin (if enabled) remains active. for spi control of power - down, the pdwn pin should be set to its default state. spi accessible featu res tab le 16 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an - 877 application note , interfacing to high speed adcs via spi . the ad9253 part - specific features are described in detail following table 17 , the external memory map register table. table 16 . features accessible using the spi feature name description power mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs, set the clock divider, set the clock divider phase, and enable the sync offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set the output clock polarity adc resolution allows for power consumption scaling with respect to sample rate.
ad9253 data sheet rev. b | page 32 of 40 memory map reading the memory m ap register table each row in the memory map register table has eight bit locations . the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the devi ce index and transfer registers (address 0x05 and address 0xff) ; and the global adc functions registers, including setup, control, and tes t (address 0x08 to address 0x109 ) . the memory map register table ( see table 17 ) lists the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x05, the device i ndex register, has a hexadecimal default value of 0x3f . this means that in addres s 0x05 , bit s [7: 6] = 0, and the remaining bits[5 :0] = 1 . this setting is the default channel index setting. the default value results in both adc channels receiving the next write command. for more information on this function and others, see the an - 877 application note , interfacing to high speed adcs via spi. this application note details the functions controlled by register 0x00 to register 0xff. the remaining registers are documented in the memory map register descriptions section. open locations all address and bit locations that are not included i n table 17 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x05). if the entire address location is open or not listed in table 17 (for example, address 0x13 ) , this address location should not be written. default values after the ad9253 is reset, critical registers are loaded with default values. the default val ues for the registers are given in the memory map register table, table 17. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel - specific registers some channel setup functions can be programmed differently for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 17 as local. these local registers and bits can be accessed by setting the appropriate data channel bits (a, b, c, or d) and the clock channel dco bit (bit 5) and fco bit (bit 4) in register 0x05. if all the bits are set, the subsequent write affects the registers of all channels and the dco/fco clock channels. in a read cycle, only one of the channels ( a, b, c, or d ) should be set to read one of the four registers. if all the bits are set during a spi read cycle, the part returns the value for channel a. registers and bits designated as global in table 17 affect the entire part or the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
data sheet ad9253 rev. b | page 33 of 40 m emory m ap r egister t able the ad9253 uses a 3 - wire interface and 16 - bit addressing and , therefore , bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1 . when bit 5 in register 0x00 is set high, the spi enter s a soft reset , where all of the user registers revert to their default values and bit 2 is automatically cleared. table 17. addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments chip configuration registers 0x00 spi port c onfiguration 0 = sdo active lsb f irst soft r eset 1 = 16 - bit address 1 = 16 - bit address soft r eset lsb f irst 0 = sdo active 0x18 the nibbles are mirrored so that lsb - first or msb - first mode register s correctly. the default for adcs is 16 - bit mode. 0x01 chip id (global) 8 - b it c hip id , bits[ 7:0 ] ad9253 0x 8f = q uad 14 - bit 80 msps /105 msps /125 msps s er ial lvds 0x8f unique chip id used to differentiate devices; read only. 0x02 chip grade (global) open speed grade id[6:4] 100 = 80 msps 101 = 105 msps 110 = 125 msps open open open open unique speed grade id used to differentiate graded devices ; r ead only. device index and transfer registers 0x05 device index open open clock channel dco clock channel fco data channel d data channel c data channel b data channel a 0x3f bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0xff transfer open open open open open open open initiate o verride 0x00 set r esolution/ s ample r ate o verride . global adc function registers 0x08 power modes (global) open open external power - down pin function 0 = full power - down 1 = standby open open open power mode 00 = chip run 01 = full power - down 10 = standby 11 = reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open open open open open open open duty cycle stabilize 0 = off 1 = on 0x01 turns duty cycle stabilizer on or off.
ad9253 data sheet rev. b | page 34 of 40 addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments 0x0b clock d ivide (global) open open open open open clock divide ratio [2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 0x0c enhancement control open open open open open chop mode 0 = off 1 = on open open 0x00 enables/ disables chop mode. 0x0d test m ode (local except for pn sequence resets) user i nput t est m ode 00 = single 01 = alternate 10 = single once 11 = alternate once (a ffects user input test mode only , bits[3:0] = 1000 ) reset pn l ong g en reset pn s hort g en output test mode [3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1 - /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, the test data is placed on the output pins in place of normal data . 0x10 offset a djust (local) 8 - bit device offset adjustment [7:0] (local) offset adjust in lsbs from +127 to ?128 (twos complement format) 0x00 device offset trim . 0x14 output mode open lvds - ansi/ lvds - ieee option 0 = lvds - ansi 1 = lvds - ieee reduced range link (global) see table 18 open open open output invert (local) open output format 0 = offset binary 1 = twos comple - ment (global) 0x01 configures the outputs and the format of the data. 0x15 output adjust open open output driver termination [1:0] 00 = none 01 = 200 10 = 100 11 = 100 open open open output drive 0 = 1 drive 1 = 2 drive 0x00 determines lvds or other output properties. 0x16 output phase open input clock phase adjust[6:4] (value is number of input clock cycles of phase delay) see table 19 output clock phase adjust[3:0] (0000 through 1011) see table 20 0x03 on devices that use global clock divide, determines which phase of the divider output is used to supply the outp ut clock. internal latching is unaffected.
data sheet ad9253 rev. b | page 35 of 40 addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments 0x18 v ref open open open open open internal v ref adjustment digital scheme [2:0] 000 = 1.0 v p - p 001 = 1.14 v p - p 010 = 1.33 v p - p 011 = 1.6 v p - p 100 = 2.0 v p - p 0x04 select s and/or adjusts the v ref . 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 lsb. 0x1a user_patt1_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 msb. 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 lsb. 0x1c user_patt2_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 msb. 0x21 serial output data control (global) lvds output lsb first sdr/ddr one - lane/ two - lane, bit wise/ byte wise[6:4] 000 = sdr two - lane, bit wise 001 = sdr two - lane, bytewise 010 = ddr two - lane, bit wise 011 = ddr two - lane, bytewise 100 = ddr one - lane open select 2 frame serial output number of bits 00 = 16 bits 10 = 12 bits 0x30 serial stream control. default causes msb first and the native bit stream. 0x22 serial channel s tatus (local) open open open open open open channel output reset channel power - down 0x00 used to power down individual sections of a converter. 0x100 resolution/ s ample rate override open resolution/ sample rate override enable resolution 01 = 14 bits 10 = 12 bits open sample rate 000 = 20 msps 001 = 40 msps 010 = 50 msps 011 = 65 msps 100 = 80 msps 101 = 105 msps 110 = 125 msps 0x00 resolution/ sample rate override (requires transfer register , 0xff). 0x101 user i/o control 2 open open open open open open open sdio pull - down 0x 00 disables sdio pull - down. 0x102 user i/o control 3 open open open open vcm power - down open open open 0x00 vcm control. 0x109 sync open open open open open open sync next only enable sync 0x00
ad9253 data sheet rev. b | page 36 of 40 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note , interfacing to hig h speed adcs via spi . device index (register 0x05) there are certain features in the map that can be set inde - pendently for each channel, whereas other features apply globally to all channels (depending on context) regardless of which are selected. the first four bits in register 0x05 can be used to select which individual data channels are affected. the output cl ock channels can be selected in register 0x05 as well. a smaller subset of the independent feature list can be applied to those devices. transfer (register 0xff) all registers except register 0x100 are updated the moment they are written. setting bit 0 of this transfer register high initializes the settings in the adc sample rate override register (address 0x100). power modes (register 0x08) bits[7:6] open bit 5 external power - down pin function if set, the external pdwn pin initiates power - down mode. if cl ear ed , the external pdwn pin initiates standby mode. bits[4:2] open bits[1:0] power mode in normal operation (bits[1:0] = 00), all adc channels are active. in power - down mode (bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. outputs are disabled . in standby mode (bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset , except the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power - on reset). enhancement control (register 0x0c) bits[7:3] open bit 2 chop mode for applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the ad9253 is a feature that can be enabled by setting bit 2. in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2 where it can be filtered. bits[1:0] open output mode (register 0x14) bit 7 open bit 6 lvds - ansi/lvds - ieee option setting this bit chooses lvds - ieee (reduced range) option. the default setting is lvds - ansi. as described in table 18, when lvds - ansi or lvds - ieee redu ced range link is selected, the user can select the driver termination. the driver current is automatically selected to give the proper output swing. table 18 . lvds - ansi/lvds - ieee options output mode, bit 6 output mode output driver termination output driver current 0 lvds - ansi user selectable automatically selected to give proper swing 1 lvds -ieee reduced range link user selectable automatically selected to give proper swing bits[5:3] open bit 2 output invert setting this bit inverts the output bit stream. bit 1 open bit 0 output format by default, this bit is set to send the data output in twos complement format. resetting this bit changes the output mode to offset binary. output adjust (register 0x15) bits[7:6] open bits[ 5:4] output driver termination these bits allow the user to select the internal termination resistor. bits[3:1] open bit 0 output drive bit 0 of the output adjust register controls the drive strength on the lvds driver of the fco and dco outputs only. the default values set the drive to 1 while the drive can be increased to 2 by setting the appropriate channel bit in register 0x05 and then setting bit 0. these features cannot be used with the output driver termina tion select. the termination selection t akes precedence over the 2 driver strength on fco and dco when both the output driver termination and output drive are selected. output phase (register 0x16) bit 7 open bits[6:4] input clock phase adjust when the clock divider (register 0x0b) is used, the applied clock is at a higher frequency than the internal sampling clock. bits[6:4] determine at which phase of the external clock the sampling occurs. this is applicable only when the clock divider is use d. it is prohibited to select a value for bits[6:4] that is greater
data sheet ad9253 rev. b | page 37 of 40 than the value of bits[2:0], register 0x0b. see table 19 for more information. table 19 . input clock phase adjust options input clock phase adjust , bits [6:4] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 bits[3:0] output clock phase adjust table 20 . output clock phase adjust options output clock (dco), phase adjust , bits [3:0] dco phase adjustment (degrees relative to d0x/d1x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 serial output data control (register 0x21) the serial output data control register is used to program the ad9253 in various output data modes depending upon the data capture solution. table 21 describes the various serialization options available in the ad9253 . resolution/ sample rate override (register 0x100) this register is designed to allow th e user to downgrade the device ( that is, establish lower power) for applications that do not require full sample rate . settings in this register are not initialized until bit 0 of the transfer register (register 0xff) is set to 1. this function does not affect the sample rate; it affects the maximum sample rate capability of the adc, as well as the resolution. user i/o control 2 (register 0x101) bits[ 7 :1] open bit 0 sdio pull - down bit 0 can be set to disable the internal 30 k pull - down on the sdio pin, which can be used to limit the loading when many devices are connected to the spi bus. user i/o control 3 (re gister 0x102) bits[7:4] open bit 3 vcm power - down bit 3 can be set high to power down the internal vcm generator. this feature is used when applying an external reference. bits[2:0] open table 21. spi register options serialization options selected register 0x21 contents serial output number of bits (sonb) frame mode serial data mode dco multiplier timing diagram 0x30 16- bit 1 ddr two - l ane b yte wise 4 f s figure 2 (default setting) 0x20 16- bit 1 ddr two - l ane b it wise 4 f s figure 2 0x10 16- bit 1 sdr two - l ane bytewise 8 f s figure 2 0x00 16- bit 1 sdr two - l ane bitwise 8 f s figure 2 0x34 16- bit 2 ddr two - l ane bytewise 4 f s figure 4 0x24 16- bit 2 ddr two - l ane bitwise 4 f s figure 4 0x14 16- bit 2 sdr two - l ane bytewise 8 f s figure 4 0x04 16- bit 2 sdr two - l ane bitwise 8 f s figure 4 0x40 16 - bit 1 ddr one - l ane 8 f s figure 6 0x32 12- bit 1 ddr two - la ne bytewise 3 f s figure 3 0x22 12- bit 1 ddr two - l ane bitwise 3 f s figure 3 0x12 12- bit 1 sdr two - l ane bytewise 6 f s figure 3 0x02 12- bit 1 sdr two - l ane bitwise 6 f s figure 3 0x36 12- bit 2 ddr two - l ane bytewise 3 f s figure 5 0x26 12- bit 2 ddr two - l ane bitwise 3 f s figure 5 0x16 12- bit 2 sdr two - l ane bytewise 6 f s figure 5 0x06 12- bit 2 sdr two - l ane bitwise 6 f s figure 5 0x42 12- bit 1 ddr one - l ane 6 f s figure 7
ad9253 data sheet rev. b | page 38 of 40 applications information design guidelines before starting design and layout of the ad9253 as a system, it is recommended that the designer become familiar with these guidelines, which describes the special circuit connections and layout requirements that are needed for certain pins. power and ground recommendations when connecting power to the ad9253 , it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd, several different decoupling capacitors should be used to cover both high and low frequencies. place these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length. a single pcb ground plane should be sufficient when using the ad9253 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. clock stability considerations when powered on, the ad9253 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. during the initialization process, the ad9253 needs a stable clock. if the adc clock source is not present or not stable during adc power-up, it disrupts the state machine and causes the adc to start up in an unknown state. to correct this, an initialization sequence must be reinvoked after the adc clock is stable by issuing a digital reset via register 0x08. in the default configuration (internal v ref , ac-coupled input) where v ref and v cm are supplied by the adc itself, a stable clock during power-up is sufficient. in the case where v ref and/or v cm are supplied by an external source, these, too, must be stable at power-up; otherwise, a subsequent digital reset via register 0x08 is needed. the pseudo code sequence for a digital reset is as follows: spi_write (0x08, 0x03); digital reset spi_write (0x08, 0x00); can be asserted as soon as the next spi instruction, normal operation resumes after 2.9 million sample clock cycles, adc outputs 0s until the reset is complete. exposed pad thermal heat slug recommendations it is required that the exposed pad on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9253 . an exposed continuous copper plane on the pcb should mate to the ad9253 exposed pad, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder-filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. see figure 75 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . silkscreen p a rtition pin 1 indicator 10065-080 figure 75. typical pcb layout vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor. reference decoupling the vref pin should be externally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9253 to keep these signals from transitioning at the con- verter inputs during critical sampling periods.
data sheet ad9253 rev. b | page 39 of 40 crosstalk performance the ad9253 is available in a 48-lead lfcsp package with the input pairs on either corner of the chip. see figure 9 for the pin configuration. to maximize the crosstalk performance on the board, add grounded filled vias in between the adjacent channels as shown in figure 76. grounded filled vias for added crosstalk isolation vin channel b vin channel c vin channel a vin channel d pin 1 10065-088 figure 76. layout technique to maximize crosstalk performance
ad9253 data sheet rev. b | page 40 of 40 outline dimensions 1 0.50 bsc bot t om view top view pin 1 indic a t or 48 13 24 36 37 exposed pa d pin 1 indic a t or * 5.70 5.60 sq 5.50 0.50 0.40 0.30 se a ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.20 10-24-2013-d 7.10 7.00 sq 6.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min * compliant to jedec standards mo-220-wkkd-2 with the exception of the exposed pad dimension. figure 77 . 48 - lead lead frame chip scale package [lfcsp_wq] 7 mm 7 mm body, very very thin quad (cp - 48 - 13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9253bcpz -80 ? 40c to +85c 48- lead lead frame chip scale package (lfcsp_wq) cp -48-13 ad9253bcpzrl7 - 80 ? 40c to +85c 48- lead lead frame chip scale package (lfcsp_wq) cp -48-13 ad9253bcpz - 105 ? 40c to +85c 48 - lead lead frame chip scale package (lfcsp_wq) cp - 48 - 13 ad9253bcpzrl7 - 105 ? 40c to +85c 48- lead lead frame chip scale package (lfcsp_wq) cp -48-13 ad9253bcpz -125 ? 40c to +85c 48- lead lead frame chip scale package (lfcsp_wq) cp -48-13 ad9253bcpzrl7 - 125 ? 40c to +85c 48- lead lead frame chip scale package (lfcsp_wq) cp -48-13 ad9253 - 125ebz evaluation board 1 z = rohs compliant part. ? 2011 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10065 - 0 - 10/15(b)

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